The formation of integrated circuits includes the definition of isolation regions to prevent parasitic current leakage between devices. Isolation techniques include the shallow trench isolation (STI) scheme that has increased the planarity and packing density of silicon very large scale integration (Si VLSI) devices, and has thus been the isolation scheme of choice since approximately the 0.25 micrometer (μm) technology node.
In a typical STI process, an active device area is protected by a pad oxide and a nitride overlayer, and isolation trenches are etched around the active device area. After the trench etch, a liner oxide is formed in each trench. This liner oxidation step serves several purposes. First, the oxidation eliminates any etch damage to a trench sidewall by consuming a small amount of the sidewall material. Second, the liner oxidation rounds the upper corners of the trench, minimizing the fringing fields that can result from sharp corners at the active area edge. If present, these fields form a parasitic, low-threshold voltage transistor at the active area edge that can degrade the subthreshold characteristics of the main device. Finally, because it is typically a thermal oxide, the liner oxide forms a high-quality interface between the Si trench sidewall and the deposited trench oxide. Interface traps, i.e., electrically active defects present at an oxide/semiconductor interface, are thereby minimized at this interface. The liner oxidation is often performed at high temperatures, i.e., >1000° C., and in an oxygen, i.e., dry ambient.
After the liner oxidation, a chemical vapor deposited (CVD) dielectric, such as silicon dioxide, is deposited over the entire substrate, filling the trenches. This CVD dielectric also covers the active device regions, and it should be selectively removed for device processing to continue. This is accomplished by planarizing the substrate, typically via chemical-mechanical polishing (CMP), using the silicon nitride layer over the active area as a stop layer. This process removes the dielectric from the active areas while retaining it in the isolation trenches. The nitride and pad oxide masking layers are then removed, resulting in a highly planar substrate with isolated device regions.
The formation of STI structures on silicon-germanium (SiGe) virtual substrates may be particularly challenging. SiGe virtual substrates are a platform for new generations of VLSI devices that exhibit enhanced performance in comparison to devices fabricated on bulk Si substrates. An important component of a SiGe virtual substrate is a layer of SiGe that has been relaxed to its equilibrium lattice constant, i.e., a lattice constant that is larger than that of Si. This relaxed SiGe layer may be formed directly on a Si substrate by, e.g., wafer bonding or direct epitaxy, or atop a relaxed graded SiGe layer, in which the lattice constant of the SiGe material has been increased gradually over the thickness of the layer. The SiGe virtual substrate can also incorporate buried insulating layers, echoing the structure of a semiconductor-on-insulator (SOI) wafer. In order to fabricate high-performance devices on these platforms, thin strained layers of Si, Ge, or SiGe are grown on the relaxed SiGe virtual substrates. The resulting biaxial tensile or compressive strain alters the carrier mobilities in the layers, enabling the fabrication of high speed and/or low power devices. Many issues and challenges arise when fabricating devices on SiGe rather than bulk Si substrates.
Forming an STI structure on a SiGe virtual substrate includes the etching and exposure of the underlying relaxed SiGe. Direct thermal liner oxidation of a trench etched in SiGe may be problematic and may result in a low-quality liner oxide. During liner oxidation, the Ge in the SiGe may be snowplowed ahead of an oxidation front, resulting in a pure silicon dioxide (SiO2) oxide layer atop a portion of a SiGe layer that is enriched in Ge content in comparison to the SiGe bulk material. Although in this case, the oxide itself has all of the properties of oxidized Si, it is proximate a layer of SiGe with an elevated Ge content. The presence of this elevated level of Ge at this interface may result in a very high density of interface traps. These interface traps may in turn result in increased subthreshold leakage, or in a shift in threshold voltage, for the active device, and are therefore undesirable.
If a trench is relied upon to induce all of the strain in a channel, the amount of strain that can be induced in the channel is limited. Too much trench-induced strain may produce defects, leading to problems with device operation.